U.S. Pat. No. 4,933,847 application Ser. No. 07/121,443, filed Nov. 17, 1987, "Microcode Branch Based of Operand Length and Alignment" is incorporated in this patent by reference.
One commonly employed technique for debugging software is the use of "breakpoints" which are set by changing the operation code byte of an instruction to a special breakpoint instruction, or simply to an invalid instruction. When this point in the program is reached, a trap is performed to a software routine which notifies the operator that the breakpoint has been reached and may additionally function to save the contents of some specified registers. This technique suffers from the disadvantages that the processor does not stop, and therefore it is not possible to perform a comprehensive analysis of the state of the system at the time of the stop.
Another technique is implemented with special purpose hardware which compares a desired stop address with the current control store address. When the hardware detects identity between the current control store address and the desired stop address, the system is brought to a halt. This overcomes some of the limitations of the system previously described, but nevertheless suffers from the inability to specify a plurality of stop addresses. Additionally, if the control store address specified is one from which an overlaid control word is executed, many false stops will result.
While it is desirable to have a service processor handle such control store stops, the service processor is not commonly attached directly to the system processor (CPU), and therefore does not have the ability to determine the current control store address nor can it inhibit the processor clock to stop the system.
U.S. Pat. No. 3,813,531 described a system in which switches connected to the instruction register may be set to a bit pattern corresponding to the instruction type to be tested. When this instruction type is present in the command or operation code register, the comparison circuit causes the system to come to a halt. This system lacks the capability of specifying the control storage address at which the system is to be stopped.
U.S. Pat. No. 4,095,268 relates to a microprogrammed system in which start and stop signals from a control console are used to start and stop operation of the system. When the system is stopped, it is possible to write selected data into specified addresses for analysis. This system does not accommodate the stopping of the system at a particular microinstruction address.
U.S. Pat. No. 4,422,144 describes a microprogrammed data processing system in which microinstructions stored in a writable control storage element may be substituted for defective microinstructions found in the read only storage element. A provision is made for the substitution of the valid microinstruction for the invalid microinstruction based on the existence of a data bit in a halt array. This array is accessed with the same address as the microinstruction and the detection of a binary one, previously stored by service personnel, causes the alternate microinstruction from the writable control storage to be executed. This system does not bring the system to a halt and contains no provision for the storage of the microinstruction originally at the control storage address where it is desired to halt.
U.S. Pat. No. 4,275,441 describes a microprogrammed processing system in which the processor can be operated a single step at a time. There is no ability to stop at a particular microinstruction address.
U.S. Pat. No. 4,392,208 describes a data processing system in which an address register may be set to an address at which it is desired to stop the system. When an address comparison circuit detects equivalence between the address used for control storage access and the desired address, the system is brought to a halt. This system does not provide for the substitution of a clock stop instruction for the normal microinstruction at the selected address in control storage.
U.S. Pat. No. 4,545,030 relates to a power conservation system for a microprocessor based system. The system is placed in the "on" state in response to various control signals such as I/O generated interrupts and placed in the "off" state in response to corresponding completion signals. There is no provision for stopping the system in response to access of particular addresses in control storage.
U.S. Pat. No. 4,530,050 describes a data processing system having a processor which is capable of executing variable length instructions. The error detection system described in the patent does not provide means for bringing the system to a halt in response to the accessing of a particular address in control storage.
U.S. Pat. No. 4,571,677 describes a tracing system for detecting the equivalence of a predetermined memory address with the current address in the memory address register of the CPU. The system does not describe means for substituting a stop clock instruction for a microinstruction at a predetermined address.
U.S. Pat. No. 4,570,218 describes a system for the transfer of data between a peripheral device and a microprocessor memory utilizing direct memory access and programmable stop codes written into data memory. There is no teaching of a system in which microinstructions are removed from control storage and replaced with clock stop instructions.
U.S. Pat. No. 4,589,065 describes a Primitive Instruction Set Machine having a trap instruction which provides a one cycle method for checking a condition and continuing execution of the instruction stream in parallel. The patent does not describe a system in which a microinstruction at a desired address is replaced with a clock stop instruction.
U.S. Pat. No. 4,598,364 describes a tracing system in which the trace instructions are permanently lodged in the program and may be selectively enabled by displacement bits. There is no description of a system which allows a microinstruction at a desired control storage address to be replaced with a stop clock instruction and subsequently restored to control storage.
U.S. Pat. No. 4,638,452 describes a data processing system in which debugging is accomplished with the aid of breakpoints which may be selectively acted upon in accordance with the nature of signals received from a peripheral device. There is no description of a system in which a microinstruction in control storage is replaced with a stop clock instruction.
U.S. Pat. No. 4,638,452 relates to a real time interrupt system microprocessor. The interrupt interval is based on the passage of real time and is not dependent on the control storage address.
IBM Technical Disclosure Bulletin, "Data Processor Fault Analysis Assist", Vol. 20, No. 6, November, 1977, p. 2193, describes a microprogrammed system which can be stopped at the end of a preselected microinstruction by means of an address matching mechanism. The system provides the ability to achieve the stop at any one of the plurality of clock pulse intervals. There is no description of a stop instruction which replaces the instruction at the preselected stop point.
IBM Technical Disclosure Bulletin, "Microcode Transparent Virtual Control Store Addressing", Vol. 29, No. 12, May, 1987, pp. 5334-5337, describes a system for determination of whether a normally non-resident module is resident in control storage, transparent to the microcode. The system described is used in the implementation of the invention described and claimed herein. The description in the TDB publication will be helpful in understanding the application of this invention to a system with virtual addressing of microcode.